M25P16-VMN6G 데이터 시트보기 (PDF) - Numonyx -> Micron

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M25P16-VMN6G

16 Mbit, serial Flash memory, 75 MHz SPI bus interface

Numonyx -> Micron 

Initial delivery state

M25P16

Figure 21. Power-up timing

VCC

VCC(max)

Program, Erase and Write commands are rejected by the device

Chip selection not allowed

VCC(min)

Reset state

of the

device

VWI

tVSL

Read access allowed

Device fully

accessible

tPUW

Table 8. Power-up timing and VWI threshold

Symbol

Parameter

tVSL(1)

tPUW(1)

VWI(1)

VCC(min) to S Low

Time delay to Write instruction

Write Inhibit voltage

1. These parameters are characterized only.

time

AI04009C

Min Max Unit

30

µs

1

10

ms

1.5

2.5

V

8

Initial delivery state

The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte

contains FFh). The Status Register contains 00h (all Status Register bits are 0).

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