R5F3640KCDFA 데이터 시트보기 (PDF) - Renesas Electronics
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R5F3640KCDFA Datasheet PDF : 91 Pages
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M16C/64C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
5.3.4 Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode)
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.3.4.1 In No Wait State Setting
Table 5.55 Memory Expansion and Microprocessor Modes (in No Wait State Setting)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
td(DB-WR)
th(WR-DB)
Parameter
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR) (3)
Measuring
Condition
Standard
Min.
Max.
30
0
0
(Note 2)
30
0
25
See
−4
Figure 5.27
30
0
30
0
40
(Note 1)
(Note 4)
Notes:
1. Calculated according to the BCLK frequency as follows:
0----.-5----×-----1---0----9 – 40[ns]
f(BCLK)
f(BCLK) is 12.5 MHz or less.
2. Calculated according to the BCLK frequency as follows:
0----.-5----×-----1---0----9 – 15[ns]
f(BCLK)
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1 − VOL/VCC2)
DBi
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ,
hold time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
4. Calculated according to the BCLK frequency as follows:
0----.-5----×-----1---0----9 – 25[ns]
f(BCLK)
Hold time is equal to or less than 0 ns when the BCLK frequency exceeds 20 MHz.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
C
R01DS0016EJ0100 Rev.1.00
Feb 07, 2011
Page 81 of 88
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