DSPIC30F9013AT-20E/ML-ES 데이터 시트보기 (PDF) - Microchip Technology

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DSPIC30F9013AT-20E/ML-ES

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC30F3014/4013

FIGURE 16-2:

UART RECEIVER BLOCK DIAGRAM

Internal Data Bus

16

Read

Write

Read Read

Write

UxMODE

UxSTA

URX8 UxRXREG Low Byte

Receive Buffer Control

– Generate Flags

– Generate Interrupt

– Shift Data Characters

LPBACK

From UxTX

1

UxRX

or UxARX

if ALTIO=1

0

· Start bit Detect

· Parity Check

· Stop bit Detect

· Shift Clock Generation

· Wake Logic

8-9

Load RSR

to Buffer

Receive Shift Register

(UxRSR)

16 Divider

Control

Signals

16x Baud Clock from

Baud Rate Generator

UxRXIF

DS70138E-page 98

© 2007 Microchip Technology Inc.

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