CS8422 데이터 시트보기 (PDF) - Cirrus Logic
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CS8422 Datasheet PDF : 82 Pages
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CS8422
Parameter
Symbol Min
Typ
Max Units
TDM Mode OSCLK Falling Edge to OLRCK Edge
tfsm
-
VL = 1.8 V, 2.5 V
-
4.2
ns
RMCK/MCLK_OUT Output Frequency (VL = 1.8 V)
-
-
13.5
MHz
RMCK/MCLK_OUT Output Frequency (VL = 2.5 V)
-
-
31
MHz
RMCK/MCLK_OUT Output Duty Cycle (VL = 1.8 V)
37
50
63
%
RMCK/MCLK_OUT Output Duty Cycle (VL = 2.5 V)
45
50
55
%
Slave Mode
ISCLK Frequency
-
-
49.152 MHz
ISCLK High Time
ISCLK Low Time
OSCLK Frequency
tsckh
9.2
tsckl
9.2
-
-
-
ns
-
-
ns
-
15.7
MHz
OSCLK High Time
tsckh
28.7
-
-
ns
OSCLK Low Time
tsckl
28.7
-
-
ns
I/OLRCK Edge to I/OSCLK Rising Edge
tlcks
7.4
-
-
ns
I/OSCLK Rising Edge to I/OLRCK Edge
tlckd
6.2
-
-
ns
OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid
tdpd
-
-
29.5
ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
tds
4.7
-
-
ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
tdh
7.3
-
-
ns
TDM Mode OLRCK High Time (Note 10)
tlrckh
20
-
-
ns
TDM Mode OLRCK Rising Edge to OSCLK Rising Edge
tfss
7.0
-
-
ns
TDM Mode OSCLK Rising Edge to OLRCK Falling Edge
tfsh
6.2
-
-
ns
Master Mode (Note 11)
I/OSCLK Frequency (non-TDM Mode)
48*Fsi/o
-
128*Fsi/o MHz
I/OLRCK Duty Cycle
45
-
55
%
I/OSCLK Duty Cycle
45
-
55
%
I/OSCLK Falling Edge to I/OLRCK Edge
tlcks
-
OSCLK Falling Edge to SDOUT Output Valid (VL = 1.8 V)
tdpd
-
OSCLK Falling Edge to SDOUT Output Valid (VL = 2.5 V)
tdpd
-
SDIN Setup Time Before I/OSCLK Rising Edge
tds
4.7
SDIN Hold Time After I/OSCLK Rising Edge
tdh
7.3
TDM Mode OSCLK Frequency (Note 12)
-
-
5.7
ns
-
11.2
ns
-
6.4
ns
-
-
ns
-
-
ns
-
31
MHz
TDM Mode OSCLK Falling Edge to OLRCK Edge (VL = 1.8V) tfsm
-
TDM Mode OSCLK Falling Edge to OLRCK Edge (VL = 2.5V) tfsm
-
Notes:
-
9.6
ns
-
5.7
ns
7. After powering up the CS8422, RST should be held low until the power supplies and clocks are settled.
8. If ISCLK is selected as the clock source for the PLL, then the Sample Rate = ISCLK/64.
18
DS692F1
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