CS8420-CSZ 데이터 시트보기 (PDF) - Cirrus Logic

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CS8420-CSZ

Digital Audio Sample Rate Converter

Cirrus Logic 

CS8420

13.4 Hardware Mode 3 Description

(Transceive Data Flow, with SRC)

Hardware Mode 3 data flow is shown in Figure 26. Audio data is input via the AES3 receiver, and rate con-

verted. The audio data at the new rate is then output via the serial audio output port. Different audio data,

synchronous to OMCK, may be input into the serial audio input port, and output via the AES3 transmitter.

The channel status data, user data, and validity bit information are handled in two alternative modes: 3A

and 3B, determined by a start-up resistor on the COPY pin. In mode 3A, the received PRO, COPY, ORIG,

and AUDIO channel status bits are output on pins. The transmitted channel status bits are copied from the

received channel status data, and the transmitted U and V bits are zero.

In mode 3B, only the COPY, and ORIG pins are output, and reflect the received channel status data. The

transmitted channel status bits, user data, and validity bits are input serially via the PRO/C, EMPH/U, and

AUDIO/V pins. Figure 20 shows the timing requirements.

The serial audio input port is always a slave.

If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample will be held.

Start-up options are shown in Table 12, and allow choice of the serial audio output port as a master or slave,

whether TCBL is an input or an output, the serial audio ports formats, and the source of the transmitted C,

U, and V data. The following pages contain the detailed pin descriptions for Hardware mode 3.

VD+

VD+

DFC0 DFC1 H/S

OSCLK

ISCLK

SDOUT OLRCK ILRCK SDIN

Output

Clock

Source

OMCK

RXP

RXN

Clocked by

Input Derived Clock

Serial

Clocked by

Output Clock

Audio

Output

AES3 Rx

&

Decoder

Sample

Rate

Converter

Serial

Audio

Input

AES3

Encoder

& Tx

C & U bit Data Buffer

TXP

TXN

RMCK RERR

PRO/C COPY ORIG EMPH/U AUDIO/V TCBL

Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)

are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.

Figure 26. Hardware Mode 3 - Transceive Data Flow, with SRC

DS245F4

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