CS8420-DSZR 데이터 시트보기 (PDF) - Cirrus Logic

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CS8420-DSZR

Digital Audio Sample Rate Converter

Cirrus Logic 

CS8420

10.6 Serial Audio Input Port Data Format (05h)

7

SIMS

SIMS

6

SISF

5

SIRES1

4

SIRES0

3

SIJUST

Master/Slave Mode Selector

0 - Serial audio input port is in Slave mode (default)

1 - Serial audio input port is in Master mode

2

SIDEL

1

SISPOL

0

SILRPOL

SISF

ISCLK frequency (for Master mode)

0 - 64*Fsi (default)

1 - 128*Fsi

SIRES[1:0]

Resolution of the input data, for right-justified formats

00 - 24 bit resolution (default)

01 - 20 bit resolution

10 - 16 bit resolution

11 - Reserved

SIJUST

Justification of SDIN data relative to ILRCK

0 - Left-Justified (default)

1 - Right-Justified

SIDEL

Delay of SDIN data relative to ILRCK, for left-justified data formats

0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (default)

1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge

SISPOL

ISCLK clock polarity

0 - SDIN sampled on rising edges of ISCLK (default)

1 - SDIN sampled on falling edges of ISCLK

SILRPOL

ILRCK clock polarity

0 - SDIN data is for the left channel when ILRCK is high (default)

1 - SDIN data is for the right channel when ILRCK is high

38

DS245F4

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