CS8420-DSZR 데이터 시트보기 (PDF) - Cirrus Logic

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CS8420-DSZR

Digital Audio Sample Rate Converter

Cirrus Logic 

CS8420

Tth

TCBL

In or Out

VLRCK

VCU

Input

Tsetup

Thold

VCU[0]

VCU[1]

VCU[2]

VCU[3]

VCU[4]

SDIN

Input

Data[4]

TXP(N) Z Data[0]

TCBL

Tth

In or Out

VLRCK

Data[5]

Data[6]

Data[7]

Data[8]

Y Data[1]

X Data[2]

Y Data[3]

X Data[4]

AES3 Transmitter in Stereo Mode

Tsetup = > 7.5 % AES3 frame time

Thold = 0

Tth > 3 OMCK if TCBL is Input

U

Input

U[0]

U[2]

SDIN

Input

Data[4]

Data[5]

TXP(N) Z

Output

Data[0]*

*Assume MMTLR = 0

Data[6]

Data[7]

Y

Data[2]*

TXP(N)

Output

Z

Data[1]*

*Assume MMTLR = 1

Y

Data[3]*

AES3 Transmitter in Mono Mode

Data[8]

X

Data[4]*

X

Data[5]*

Tsetup = > 15 % AES3 frame time

Thold = 0

Tth > 3 OMCK if TCBL is Input

VLRCK is a virtual word clock, which may not exist, and is used to illustrate CUV timing.

VLRCK duty cycle is 50%

In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate.

If the serial audio input port is .in slave mode and TCBL is an output, the VLRCK=ILRCK if SILRPOL=0 and

VLRCK = ILRCK if SILRPOL = 1.

If the serial audio input port is in master mode and TCBL is an input, the VLRCK=ILRCK if SILRPOL=0 and

VLRCK= ILRCK if SILRPOL = 1.

Figure 20. AES3 Transmitter Timing for C, U and V Pin Input Data

26

DS245F4

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