CS8416-CS 데이터 시트보기 (PDF) - Cirrus Logic

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CS8416-CS

192 kHz Digital Audio Interface Receiver

Cirrus Logic 

CS8416

8.7 Receiver Error Mask (06h)

7

6

5

4

3

2

1

0

0

QCRCM

CCRCM

UNLOCKM

VM

CONFM

BIPM

PARM

The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a

mask bit is set to 1, the error is unmasked, meaning that its occurrence will appear in the receiver

error register, will affect the RERR pin, will affect the RERR interrupt, and will affect the current audio

sample according to the status of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning

that its occurrence will not appear in the receiver error register, will not affect the RERR pin, will not

affect the RERR interrupt, and will not affect the current audio sample. The CCRC and QCRC bits

behave differently from the other bits: they do not affect the current audio sample even when un-

masked. This register defaults to 00h.

8.8 Interrupt Mask (07h)

7

6

5

4

3

2

1

0

0

PCCHM

OSLIPM

DETCM

CCHM

RERRM

QCHM

FCHM

The bits of this register serve as a mask for the Interrupt Status register. If a mask bit is set to 1, the

error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask

bit is set to 0, the error is masked, meaning that its occurrence will not affect the internal INT signal

or the status register. The bit positions align with the corresponding bits in Interrupt Status register.

This register defaults to 00h.

The INT signal may be selected to appear on the GPO pins.

8.9 Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h)

7

6

5

4

3

2

1

0

0

PCCH1

OSLIP1

DETC1

CCH1

RERR1

QCH1

FCH1

0

PCCH0

OSLIP0

DETC0

CCH0

RERR0

QCH0

FCH0

The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There

are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge

active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge

active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active

mode, the INT interrupt pin becomes active during the interrupt condition. Be aware that the active

level(Active High or Low) only depends on the INT[1:0] bits. These registers default to 00h.

00 - Rising edge active

01 - Falling edge active

10 - Level active

11 - Reserved

DS578PP2

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