CS8403A-CS 데이터 시트보기 (PDF) - Cirrus Logic
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CS8403A-CS Datasheet PDF : 33 Pages
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CS8403A CS8404A
When FSYNC is a word clock (Format 2), CBL is
sampled when left C, U, V are sampled. When
FSYNC is Left/Right, CBL is sampled when left C,
U, V are sampled. The channel status block bound-
ary is reset when CBL transitions from low to high
(based on two successive samples of CBL). MCK
for the CS8404A is normally expected to be 128
times the sample frequency, in the transparent
mode MCK must be 256 Fs.
Professional Mode
Setting PRO low places the CS8404A in profes-
sional mode as shown in Figure 19. In professional
mode, channel status bit 0 is transmitted as a one
and bits 1, 2, 3, 4, 6, 7, and 9 can be controlled via
dedicated pins. The pins are actually the inverse of
the identified bit. For example, tying the C1 pin
low places a one in channel status bit 1. As shown
in the Application Note (AN22), Overview of AES/
EBU Digital Audio Interface Data Structures, C1
indicates audio/non-audio; C6 and C7 determine
the sample frequency; and C9 allows the encoded
channel mode to be stereophonic. EM1 and EM0
determine emphasis and encode C2, C3, C4 as
shown in Table 4. The dedicated channel status
pins are read at the appropriate time and are logi-
cally OR’ed with data input on the channel status
port, C. In Transparent Mode, these dedicated
channel status pins are ignored and channel status
bits are input at the C pin.
EM1
EM0
C2
C3
C4
0
0
1
1
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
Table 4. Emphasis Encoding
SDATA
SCK
FSYNC
8
6
7
M2 M1 M0
23 22 21
Serial
Port
Logic
Audio
Aux
C
U
V
10
11
9
Registers
TRNPT 24
C Bits
CRC
U Bits
Validity
Preamble
Biphase
Mark
Encoder
Mux
Timing
Line
Driver
20 TXP
17 TXN
16 RST
Parity
2 14 13 3 4 1 12
PRO EM0 EM1 C1 C6 C7 C9
15 5
CBL MCK
Figure 19. CS8404A Block Diagram - Professional Mode
DS239PP1
23
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