CS5571-ISZ 데이터 시트보기 (PDF) - Cirrus Logic

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CS5571-ISZ

±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ∆Σ ADC

Cirrus Logic 

3/25/08

10:56

CS5571

3.14 Synchronizing Multiple Converters

Many measurement systems have multiple converters that need to operate synchronously. The convert-

ers should all be driven from the same master clock. In this configuration, the converters will convert syn-

chronously if the same CONV signal is used to drive all the converters, and CONV falls on a falling edge

of MCLK. If CONV is held low continuously, reset (RST) can be used to synchronize multiple converters

if RST is released on a falling edge of MCLK.

DS768PP1

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