CS5566(2008) 데이터 시트보기 (PDF) - Cirrus Logic

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CS5566
(Rev.:2008)

±2.5 V / 5 V, 5 kSps, 24-bit ∆Σ ADC

Cirrus Logic 

3/26/08

CS5566

4. PIN DESCRIPTIONS

Chip Select

CS 1

Factory Test

TST 2

Serial Mode Select SMODE 3

Differential Analog Input

AIN+ 4

Differential Analog Input

AIN- 5

Negative Power 1

V1- 6

Positive Power 1

V1+ 7

Buffer Enable BUFEN 8

Voltage Reference Input VREF+ 9

Voltage Reference Input VREF- 10

Bipolar/Unipolar Select BP/UP 11

Sleep Mode Select SLEEP 12

24

RDY Ready

23

SCLK Serial Clock Input/Output

22

SDO Serial Data Output

21

VL

Logic Interface Power

20

VLR Logic Interface Return

19

MCLK Master Clock

18

V2-

Negative Voltage 2

17

V2+

Positive Voltage 2

16

DCR Digital Core Regulator

15

CONV Convert

14

VLR2 Logic Interface Return

13

RST Reset

CS – Chip Select, Pin 1

The Chip Select pin allows an external device to access the serial port. If SMODE = VL (SSC

Mode) and CS is held high, the SDO output and the SCLK output will be held in a

high-impedance output state.

TST – Factory Test, Pin 2

Factory test only. Connect to VLR.

SMODE – Serial Mode Select, Pin 3

The serial interface mode pin (SMODE) dictates whether the serial port behaves as a master or

slave interface. If SMODE is tied high (to VL), the port will operate in the Synchronous

Self-Clocking (SSC) mode. In SSC mode, the port acts as a master in which the converter out-

puts both the SDO and SCLK signals. If SMODE is tied low (to VLR), the port will operate in the

Synchronous External Clocking (SEC) mode. In SEC mode, the port acts as a slave in which

the external logic or microcontroller generates the SCLK used to output the conversion data

word from the SDO pin.

AIN+, AIN- – Differential Analog Input, Pin 4, 5

AIN+ and AIN- are differential inputs for the converter.

V1- – Negative Power 1, Pin 6

The V1- and V2- pins provide a negative supply voltage to the core circuitry of the chip. These

two pins should be decoupled as shown in the application block diagrams. V1- and V2- should

be supplied from the same source voltage. For single-supply operation, these two voltages are

nominally 0 V (Ground). For dual-supply operation, they are nominally -2.5 V.

V1+ – Positive Power 1, Pin 7

The V1+ and V2+ pins provide a positive supply voltage to the core circuitry of the chip. These

two pins should be decoupled as shown in the application block diagrams. V1+ and V2+ should

be supplied from the same source voltage. For single supply-operation, these two voltages are

nominally +5 V. For dual-supply operation, they are nominally +2.5 V.

BUFEN – Buffer Enable, Pin 8

Buffers on input pins AIN+ and AIN- are enabled if BUFEN is connected to V1+ and disabled if

connected to V1-.

VREF+, VREF- – Voltage Reference Input, Pin 9, 10

A differential voltage reference input on these pins functions as the voltage reference for the

converter. The voltage between these pins can range between 2.4 volts and 4.2 volts, with

4.096 volts being the nominal reference voltage value.

26

DS806PP1

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