CS5560(2008) 데이터 시트보기 (PDF) - Cirrus Logic

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CS5560
(Rev.:2008)

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC

Cirrus Logic 

3/25/08

CS5560

MCLK

RDY

t15

CS

t21

t20

SCLK(i)

t17

t18 t19

SDO

MSB

LSB

Figure 4. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale)

DIGITAL CHARACTERISTICS

TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V

Parameter

Input Leakage Current

Digital Input Pin Capacitance

Digital Output Pin Capacitance

Symbol

Min

Typ Max Unit

Iin

-

-

2

µA

Cin

-

3

-

pF

Cout

-

3

-

pF

DIGITAL FILTER CHARACTERISTICS

TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V

Parameter

Symbol Min

Group Delay

-

-

Typ

Max Unit

160

- MCLKs

10

DS713PP1

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