CS5560(2008) 데이터 시트보기 (PDF) - Cirrus Logic

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CS5560
(Rev.:2008)

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC

Cirrus Logic 

3/25/08

CS5560

Figure 17 illustrates the noise floor of the converter from 0.1 Hz to 25 kHz. While the plot does exhibit

some 1/f noise at lower frequencies, the noise floor is entirely free of spurious frequency content due to

digital activity inside the chip.

Figure 16 illustrates a noise histogram of 32,768 samples.

-60

-80

-100

-120

-140

-160

-180

0.1

Shorted Input

1M Samples @ 50 kSps

64 Averages

1

10

100

1k

Frequency (Hz)

Figure 17. Spectral Plot of Noise with Shorted Input

10k 25k

800

700

600

Std. Dev. = 19.0

Max - Min = 178

500

400

300

200

100

0

Output (Codes)

Figure 18. Noise Histogram (32k Samples)

22

DS713PP1

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