CS5525-AS 데이터 시트보기 (PDF) - Cirrus Logic

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CS5525-AS

16-bit/20-bit, Multi-range ADC with 4-bit Latch

Cirrus Logic 

CS5525 CS5526

CS

SCLK

SDI

Command Time

8 SCLKs

MSB

LSB

Data Tim e 24 SCLKs

(or 72 SC LKs for Set-up R egisters)

W rite Cycle

CS

SCLK

SDI

SDO

Command Time

8 SCLKs

MSB

LSB

Data Time 24 SCLKs

(or 72 SC LKs for Set-up Registers)

Read Cycle

SCLK

SDI

SDO

Command Time

8 SCLKs

td*

8 SC LKs C lear S DO Flag MSB

X IN /OW R

Clock C ycles

LSB

* td = XIN /O W R clock cycles for each conversion except the

first conversion w hich w ill take X IN /O W R + 7 clock cycles

Data Time

24 SCLKs

SDO Continuous Conversion Read (PF bit = 1)

Figure 6. Command and Data Word Timing.

DS202F5

13

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