CS53L21-DNZR 데이터 시트보기 (PDF) - Cirrus Logic

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CS53L21-DNZR

Low Power, Stereo Analog to Digital Converter

Cirrus Logic 

CS53L21

4.10 Software Mode

The control port is used to access the registers allowing the A/D to be configured for the desired operational

modes and formats. The operation of the control port may be completely asynchronous with respect to the

audio sample rates. However, to avoid potential interference problems, the control port pins should remain

static if no operation is required.

The control port operates in two modes: SPI and I²C, with the A/D acting as a slave device. Software Mode

is selected if there is a high-to-low transition on the AD0/CS pin after the RESET pin has been brought high.

I²C Mode is selected by connecting the AD0/CS pin through a resistor to VL or DGND, thereby permanently

selecting the desired AD0 bit address state.

4.10.1 SPI Control

In Software Mode, CS is the CS53L21 chip-select signal, CCLK is the control port bit clock (input into the

CS53L21 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked

in on the rising edge of CCLK. The A/D will only support write operations. Read request will be ignored.

Figure 18 shows the operation of the control port in Software Mode. To write to a register, bring CS low.

The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write

indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),

which is set to the address of the register that is to be updated. The next eight bits are the data which will

be placed into the register designated by the MAP.

There is MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,

the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment

after each byte is read or written, allowing block reads or writes of successive registers.

CS

CCLK

CDIN

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +n

1 0 0 1 0 1 0 0 INCR 6 5 4 3 2 1 0 7 6

10 7 6

10

Figure 18. Control Port Timing in SPI Mode

4.10.2 I²C Control

In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.

There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected

through a resistor to VL or DGND as desired. The state of the pin is sensed while the CS53L21 is being

reset.

The signal timings for a read and write cycle are shown in Figure 19 and Figure 20. A Start condition is

defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while

the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the

CS53L21 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low

for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a

CS53L21, the chip address field, which is the first byte sent to the CS53L21, should match 100101 fol-

lowed by the setting of the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write,

the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the

operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-

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DS700PP1

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