CS5376A-IQ(2004) 데이터 시트보기 (PDF) - Cirrus Logic

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CS5376A-IQ
(Rev.:2004)

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376A

Instruction

Write

Read

Opcode

0x02

0x03

Address

SPI2CMD[7:0]

SPI2CMD[7:0]

Definition

Write serial peripheral beginning at the address

given in SPI2CMD[7:0].

Read serial peripheral beginning at the address

given in SPI2CMD[7:0].

SPI 2 Write to External Slave

SPI2CMD[15:8]

SPI2CMD[7:0]

SPI2DAT

SO

0x02 ADDR Data1 Data2 Data3

SI

CS

SPI 2 Read from External Slave

SPI2CMD[15:8]

SPI2CMD[7:0]

SO

0x03 ADDR

SI

Data1 Data2 Data3

SPI2DAT

CS

Figure 40. SPI 2 Master Mode Transactions

In SPI mode 3, the SCK2 serial clock is defined ini-

tially in a high state. Output data on the SO pin is

invalid until the initial falling edge of SCK2, and

the first rising edge of SCK2 latches valid data.

SPI modes 1 and 4 work similarly to modes 0 and

3, with the serial clock defined to have data valid on

falling edges and transitioning on rising edges.

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