CS5376A-IQ(2004) 데이터 시트보기 (PDF) - Cirrus Logic

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CS5376A-IQ
(Rev.:2004)

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376A

10.4 Modulator Data Inputs

The MDATA input expects 1-bit ∆Σ data at a

512 kHz or 256 kHz rate. The input rate is selected

by a bit in the CONFIG register (0x00). By default,

MDATA is expected at 512 kHz.

The MDATA input one’s density is designed for

full scale positive at 86% and full scale negative at

14%, with absolute maximum over-range capabili-

ty to 93% and 7%. These raw ∆Σ inputs are deci-

mated and filtered by the digital filter to create 24-

bit samples at the output rate.

10.5 Modulator Flag Inputs

A high MFLAG input signal indicates the corre-

sponding ∆Σ modulator has become unstable due

to an analog over-range input signal. Once the

over-range signal is reduced, the modulator recov-

ers stability and the MFLAG signal is cleared.

The MFLAG inputs are mapped to status bits in the

SD port, and are associated with each sample when

written. See “Serial Data Port” on page 61 for more

information on the MFLAG error bits in the SD

port status byte.

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