CS5371A-ISZ(2006) 데이터 시트보기 (PDF) - Cirrus Logic

부품명

상세내역

제조사

CS5371A-ISZ
(Rev.:2006)

Low-power, High-performance ∆Σ Modulators

Cirrus Logic 

CS5371A CS5372A

VA+

PWDN

INR+

INF+

INF-

INR-

VREF+

VREF-

4th Order

∆Σ Modulator

CS5371A

VA-

OFST

VD

VA+

PWDN1

MFLAG

MDATA

Clock

Generator

MCLK

MSYNC

INR1+

INF1+

INF1-

INR1-

VREF+

VREF-

INR2+

INF2+

INF2-

INR2-

4th Order

∆Σ Modulator

4th Order

∆Σ Modulator

GND

VA-

PWDN2 OFST

VD

MFLAG1

MDATA1

Clock

Generator

MCLK

MSYNC

MFLAG2

MDATA2

CS5372A

GND

Figure 10. CS5371A and CS5372A Block Diagrams

3. MODULATOR OPERATION

The CS5371A and CS5372A are one- and

two-channel, fourth-order ∆Σ modulators opti-

mized for extremely high-resolution measure-

ment of signals between DC and 2000 Hz.

When combined with CS3301A / CS3302A dif-

ferential amplifiers, the CS4373A test DAC

and CS5376A digital filter, a small, low-power,

self-testing, high-accuracy, multi-channel

measurement system results.

The CS5371A and CS5372A modulators have

high dynamic range and low total harmonic

distortion with very low power consumption

and are optimized for extremely high-resolu-

tion measurement of 5 Vp-p or smaller differen-

tial signals. They convert analog input signals

from the CS3301A / CS3302A differential am-

plifiers to an oversampled serial bit stream at

512 kbits per second which is then passed to

the digital filter.

The companion CS5376A digital filter gener-

ates the clock and synchronization inputs for

the CS5371A / CS5372A modulators while re-

ceiving the one-bit data and over-range flag

outputs. The digital filter decimates the modu-

lator’s oversampled output bit stream to a

high-resolution, 24-bit output at the selected

output word rate.

3.1 One’s Density

In normal operation a differential analog input

signal is converted to an oversampled ∆Σ seri-

al bit stream on the MDATA output, with a

one’s density proportional to the differential

amplitude of the analog input signal.

One’s density of the MDATA output is defined

as the ratio of ‘1’ bits to total bits in the serial

bit stream output, i.e. an 86% one’s density

has, on average, a ‘1’ value in 86 of every 100

output data bits. The MDATA output has a

nominal 50% one’s density for a mid-scale dif-

ferential input, approximately 86% one’s den-

sity for a positive full-scale input signal, and

approximately 14% one’s density for a nega-

tive full-scale input signal.

DS748F1

15

Share Link: