CS43L43 데이터 시트보기 (PDF) - Cirrus Logic
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CS43L43 Datasheet PDF : 36 Pages
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CS43L43
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE
(Inputs: Logic “0” = GND, Logic “1” = VL.)
Parameter
Symbol
Min
I2C Mode
SCL Clock Frequency
fscl
-
RST Rising Edge to Start
tirs
-------1-------
(2)Fs
Bus Free Time Between Transmissions
tbuf
4.7
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low time
tlow
4.7
Clock High Time
thigh
4.0
Setup Time for Repeated Start Condition
tsust
4.7
SDA Hold Time from SCL Falling
(Note 7)
thdd
0
SDA Setup time to SCL Rising
tsud
250
Rise Time of SCL
trc
-
Fall Time of SCL
tfc
-
Rise Time SDA
trd
-
Fall Time of SDA
tfd
-
Setup Time for Stop Condition
tsusp
4.7
Max
Unit
100
kHz
-
s
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
25
ns
25
ns
1
µs
300
ns
-
µs
7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Stop
S ta rt
R e p e a te d
S ta rt
SDA
t buf
t hdst
t high
t hdst
tf
SCL
t lo w t hdd
t sud
t sust
tr
Figure 22. Control Port Timing - I2C Mode
Stop
t susp
32
DS479PP3
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