CS43L21 데이터 시트보기 (PDF) - Cirrus Logic

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CS43L21

Low Power, Stereo Digital to Analog Converter

Cirrus Logic 

CS43L21

4.2 Hardware Mode

A limited feature-set is available when the D/A powers up in Hardware Mode (see “Recommended Power-

Up Sequence” section on page 31) and may be controlled via stand-alone control pins. Table 2 shows a list

of functions/features, the default configuration and the associated stand-alone control available.

Hardware Mode Feature/Function Summary

Feature/Function

Default Configuration Stand-Alone Control

Note

Power Control

Auto-Detect

Speed Mode

MCLK Divide

Device

DACx

Serial Port Slave

Serial Port Master

Serial Port Master / Slave Selection

Interface Control

DAC

DAC Volume & Gain

HP Gain

AOUTx Volume

Invert

Soft Ramp

Zero Cross

DAC De-Emphasis

Signal Processing Engine (SPE)

Mix

Beep

Tone Control

Peak Detect and Limiter

Data Selection

Channel Mix

DAC

Charge Pump Frequency

Powered Up

Powered Up

Enabled

Auto-Detect Speed Mode

Single-Speed Mode

(Selectable)

(Selectable)

(Selectable)

G = 0.6047

0 dB

Disabled

Enabled

Disabled

(Selectable)

Disabled

Disabled

Disabled

Disabled

Data Input (PCM) to DAC

PCMA = L; PCMB = R

(64xFs)/7

-

-

-

“MCLKDIV2” pin 2

“M/S” pin 29

“I²S/LJ” pin 3

-

-

-

see Section

4.4 on page 28

see Section

4.4 on page 28

see Section

4.5 on page 30

-

-

“DEM” pin 4

-

-

-

-

see Section

on page 24

-

-

-

-

Table 2. Hardware Mode Feature Summary

DS723A1

23

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