CS4373A-ISZ 데이터 시트보기 (PDF) - Cirrus Logic

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CS4373A-ISZ

Low-power, High-performance ∆Σ Test DAC

Cirrus Logic 

CS4373A

LIST OF FIGURES

Figure 1. Digital Input Rise and Fall Times ................................................................................... 12

Figure 2. System Timing Diagram................................................................................................. 14

Figure 3. MCLK / MSYNC Timing Detail ....................................................................................... 14

Figure 4. CS4373A Block Diagram ............................................................................................... 16

Figure 6. Connection Diagram ...................................................................................................... 17

Figure 5. System Diagram ............................................................................................................ 17

Figure 7. Power Mode Diagram .................................................................................................... 18

Figure 8. AC Differential Modes .................................................................................................... 19

Figure 9. AC Common Mode ........................................................................................................ 20

Figure 10. DC Test Modes ............................................................................................................ 21

Figure 11. Digital Inputs ................................................................................................................ 22

Figure 12. Analog Outputs ............................................................................................................ 24

Figure 13. Voltage Reference Circuit ............................................................................................ 26

Figure 14. Power Supply Diagram ................................................................................................ 28

LIST OF TABLES

Table 1. Selections for Operational Mode and Attenuation............................................................. 4

Table 2. Operational Modes.......................................................................................................... 19

Table 3. Output Attenuation Settings ............................................................................................ 24

DS699F2

3

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