CS4373A-ISZ 데이터 시트보기 (PDF) - Cirrus Logic

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CS4373A-ISZ

Low-power, High-performance ∆Σ Test DAC

Cirrus Logic 

CS4373A

DIGITAL CHARACTERISTICS (CONT.)

Parameter

Symbol Min

Master Clock

MCLK Frequency

MCLK Period

MCLK Duty Cycle

MCLK Rise Time

MCLK Fall Time

MCLK Jitter (In-band or aliased in-band)

MCLK Jitter (Out-of-band)

Master Sync

(Note 25) fCLK

-

(Note 25) tmclk

-

(Note 8) MCLKDC

40

(Note 8) tRISE

-

(Note 8) tFALL

-

(Note 8) MCLKIBJ

-

(Note 8) MCLKOBJ

-

MSYNC Setup Time to MCLK rising

(Note 8, 26) tmss

20

MSYNC Period

(Note 8, 26) tmsync

40

MSYNC Hold Time after MCLK falling

(Note 8, 26) tmsh

20

MSYNC Instant to TDATA Start

(Note 8, 27) ttdata

-

Typ

2.048

488

-

-

-

-

-

122

976

122

1220

Max

-

-

60

50

50

300

1

-

-

-

-

Unit

MHz

ns

%

ns

ns

ps

ns

ns

ns

ns

ns

Notes: 25. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the device automatically enters

a power-down state.

26. MSYNC is generated by the CS5376A digital filter and is latched on MCLK rising edge, synchronization

instant (t0) on next MCLK rising edge.

27. TDATA can be delayed from 0 to 63 full bit periods by the CS5376A test bit stream generator. The timing

diagram shows no TBSDATA delay.

DS699F2

13

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