CS4362ACQZR 데이터 시트보기 (PDF) - Cirrus Logic
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CS4362ACQZR Datasheet PDF : 47 Pages
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CS4362A
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Max
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
(Note 17)
fsclk
-
6
tsrs
500
-
tspi
500
-
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
(Note 18)
tcsh
1.0
-
tcss
20
-
tscl
66
-
tsch
66
-
tdsu
40
-
tdh
15
-
Rise Time of CCLK and CDIN
(Note 19)
tr2
-
100
Fall Time of CCLK and CDIN
(Note 19)
tf2
-
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Notes:
17. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
18. Data must be held for sufficient time to bridge the transition time of CCLK.
19. For FSCK < 1 MHz.
RST
t srs
CS
CCLK
CDIN
t spi t css
t scl t sch
t r2
t f2
t dsu t dh
Figure 4. Control Port Timing - SPI Format
t csh
DS617PP1
17
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