CS4362-BQ 데이터 시트보기 (PDF) - Cirrus Logic
부품명
상세내역
제조사
CS4362-BQ Datasheet PDF : 40 Pages
| |||
CS4362
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(For KQ TA = -10 to +70 °C; For BQ TA = -40 to +85 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic
1 = VLC, CL = 30 pF)
Parameter
CCLK Clock Frequency
Symbol
Min
fsclk
-
Max
M------C----L----K---
2
Unit
MHz
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
tsrs
(Note 23)
tspi
tcsh
tcss
tscl
500
500
1.0
20
--------1---------
MCLK
-
ns
-
ns
-
µs
-
ns
-
ns
CCLK High Time
tsch
--------1---------
MCLK
-
ns
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
tdsu
40
(Note 24)
tdh
15
(Note 25)
tr2
-
(Note 25)
tf2
-
-
ns
-
ns
100
ns
100
ns
Notes: 23. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
24. Data must be held for sufficient time to bridge the transition time of CCLK.
25. For FSCK < 1 MHz.
RST
t srs
CS
t spi t css
t scl t sch
t csh
CCLK
t r2
t f2
C D IN
t dsu t dh
Figure 4. Control Port Timing - SPI Format
11
Share Link: 