CS4341 데이터 시트보기 (PDF) - Cirrus Logic

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CS4341

24-Bit, 96 kHz Stereo DAC with Volume Control

Cirrus Logic 

CS4341

6. REGISTER DESCRIPTION

NOTE: All registers are read/write in I²C Mode and write only in SPI mode, unless otherwise stated.

6.1 MCLK CONTROL (ADDRESS 00H)

7

Reserved

0

6

Reserved

0

5

Reserved

0

4

Reserved

0

3

Reserved

0

2

Reserved

0

1

MCLKDIV

0

0

Reserved

0

6.1.1 MCLK DIVIDE-BY-2 (MCLKDIV) BIT 1

Default = 0

0 - Disabled

1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.

6.2 MODE CONTROL (ADDRESS 01H)

7

AMUTE

1

6

DIF2

0

5

DIF1

0

4

DIF0

0

3

DEM1

0

2

DEM0

0

1

POR

1

0

PDN

1

6.2.1 AUTO-MUTE (AMUTE) BIT 7

Default = 1

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio

samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and muting

is done independently for each channel. The quiescent voltage on the output will be retained and the

Mute Control pin will go active during the mute period. The muting function is affected, similar to vol-

ume control changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address

02h) register.

DS298F5

25

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