CS4340-DSZ 데이터 시트보기 (PDF) - Cirrus Logic
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CS4340-DSZ Datasheet PDF : 25 Pages
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CS4340
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK
Parameters
Symbol
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate
Single-Speed Mode Fs
Double-Speed Mode Fs
LRCK Duty Cycle
SCLK Period
(Note 7) tsclkw
SCLK rising to LRCK edge
tsclkr
SDATA valid to SCLK rising setup time
tsdlrs
SCLK rising to SDATA hold time
tsdh
MCLK / LRCK = 512, 256 or 128
Min
1.024
45
4
50
-------1---------
SCLK
Typ
-
-
-
-
(Note 6)
-
-
(---5---1----21---)---F----s- + 10
(---5---1----21---)---F----s- + 15
t--s---c--l--k--w--
2
-
-
Max
25.6
55
50
100
-
-
-
-
SCLK rising to SDATA hold time
tsdh
MCLK / LRCK = 384 or 192
----------1----------- + 15
( 384 ) F s
-
-
Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period.
7. See section 4.2.1 for derived internal frequencies.
LRCK
SDATA
t sclkr
t sdlrs t sdh
t sclkw
*INTERNAL SCLK
Figure 12. Internal Serial Mode Input Timing
*The SCLK pulses shown are internal to the CS4340.
LRCK
Units
MHz
%
kHz
kHz
%
s
s
ns
ns
ns
MCLK
1
N
N
2
*INTERNAL SCLK
SDATA
Figure 13. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4340. N equals MCLK divided by SCLK
12
DS297F3
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