CS4237B-JQ 데이터 시트보기 (PDF) - Cirrus Logic
부품명
상세내역
제조사
CS4237B-JQ Datasheet PDF : 114 Pages
| |||
CS4237B
interface due to transient currents during bus
switching. SGND1-4 are the substrate grounds
and should also be connected to the digital
ground plane to minimize coupling into the ana-
log section. Figure 33 shows the recommended
positioning of the decoupling capacitors. The ca-
pacitors must be on the same layer as, and close
to, the part. The vias shown go through to the
ground and power plane layers. Vias, power sup-
ply traces, and REFFLT traces should be as large
as possible to minimize the impedance.
POWER SUPPLIES
The power supply providing analog power
should be as clean as possible to minimize cou-
pling into the analog section and degrading
analog performance.
The VD1 is isolated from the rest of the power
supply pins and provide digital power for the
asynchronous parallel ISA bus (except for
DRQA). The VD1 pin can be connected directly
to the system digital power supply. VD1 can also
be connected to a 3.3V supply providing a 3.3V
ISA interface. When connected to a 3.3V supply,
all ISA bus input pins (SA15-0, SD7-0, DACKs,
etc.) must be at 3.3V levels (not 5V), with the
exception of the DRQA pin. DRQA is internally
connected to the VDF supplies and remains a
5 Volt pin even when the ISA bus is run at
3.3 Volts. When the ISA bus is powered from
3.3 Volts, DRQA can be be used through a level
translator, or DRQA can remain used. If DRQA
is not used, all references to this pin should be
removed in the PnP Resource data. Even though
the ISA bus is at 3.3V, the peripheral port is still
at a 5V potential including XD7-0 and all chip
select and address pins.
VDF1 through VDF4 provide power to internal
digital sections of the codec and should be qui-
eter than VD1. This can be achieved by using a
DS213PP4
Digital
Ground
Crystal
Part
Noise
1
Analog
Ground
Digital
Ground
Digital Ground Noise
Digital Ground Noise
Power
Connector
Figure 31. Suggested Motherboard Layout
93
Share Link: 