CL-PS7111-VC-A 데이터 시트보기 (PDF) - Cirrus Logic

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CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

The output channel is fed by an 8-bit shift register, and the input channel is captured by a 16-bit shift reg-

ister. The clock and synchronization pulses are activated by a write to the Output Shift register. During

transfers, the SSIBUSY is set. When the transfer is complete and valid data is in the 16-bit read shift reg-

ister, the SSEOTI interrupt is asserted and the SSIBUSY bit is cleared.

An additional sample clock (SMPCLK) is enabled independently and set at twice the transfer clock fre-

quency. This interface has no local buffering capabilities and is only intended to be used with low-band-

width interfaces (such as a touchscreen ADC interface).

42

FUNCTIONAL DESCRIPTION

September 1997

PRELIMINARY DATA BOOK v2.0

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