CS5345(2004) 데이터 시트보기 (PDF) - Cirrus Logic

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CS5345
(Rev.:2004)

105 dB, 24-Bit, 192 kHz Stereo Audio ADC

Cirrus Logic 

CS5345

6.10.2 Overflow (Bit 1)

Function:

Indicates the occurrence of an ADC overflow condition.

6.10.3 Underflow (Bit 0)

Function:

Indicates the occurrence of an ADC underflow condition.

6.11 Interrupt Mask - Address 0Eh

7

Reserved

6

Reserved

5

Reserved

4

Reserved

3

ClkErrM

2

Reserved

1

OvflM

0

UndrflM

Function:

The bits of this register serve as a mask for the Status sources found in the register “Interrupt Status

- Address 0Dh” on page 33. If a mask bit is set to 1, the error is unmasked, meaning that its occur-

rence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, mean-

ing that its occurrence will not affect the INT pin or the status register. The bit positions align with the

corresponding bits in the Status register.

6.12 Interrupt Mode MSB - Address 0Fh

6.13 Interrupt Mode LSB - Address 10h

7

Reserved

Reserved

6

Reserved

Reserved

5

Reserved

Reserved

4

Reserved

Reserved

3

ClkErr1

ClkErr0

2

Reserved

Reserved

1

Ovfl1

Ovfl0

0

Undrfl1

Undrfl0

Function:

The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There

are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge

active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge

active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active

mode, the INT pin remains active during the interrupt condition.

00 - Rising edge active

01 - Falling edge active

10 - Level active

11 - Reserved

34

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