CS4385(2004) 데이터 시트보기 (PDF) - Cirrus Logic
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CS4385 Datasheet PDF : 56 Pages
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CS4385
More information for any of these register bits can be found in the Register Description section.
The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50%
modulation index) at full rated performance. Signals of +3 dB-SACD may be applied for brief pe-
riods of time however, performance at these levels is not guaranteed. If sustained +3 dB-SACD
levels are required, the digital volume control should be set to -3.0 dB. This same volume control
register affects PCM output levels. There is no need to change the volume control setting be-
tween PCM and DSD in order to have the 0dB output levels match (both 0 dBFS and 0 dB-SACD
will output at -3 dB in this case).
DSD Normal Mode
Not Used
DSD Phase
Modulation Mode
DSD_SCLK
BCKA
(128Fs)
BCKA
(64Fs)
DSD_SCLK
Not Used
D0
DSDAx,
DSDBx
D0
D1
D1
D1
DSD_SCLK
BCKD
(64Fs)
D2
DSDAx,
DSDBx
D2 Not Used
Figure 22. DSD phase modulation mode diagram
3.9 Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4385 requires careful attention to power supply and
grounding arrangements if its potential performance is to be realized. The Typical Connection Di-
agram shows the recommended power arrangements, with VA, VD, VLC, and VLS connected to
clean supplies. If the ground planes are split between digital ground and analog ground, the GND
pins of the CS4385 should be connected to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid
unwanted coupling into the DAC.
26
DS671A1
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