CRD42L51(2005) 데이터 시트보기 (PDF) - Cirrus Logic
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CRD42L51 Datasheet PDF : 83 Pages
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SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL)
Parameter
CCLK Clock Frequency
RESET Rising Edge to CS Falling
CS Falling to CCLK Edge
CS High Time Between Transmissions
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 19)
(Note 20)
(Note 20)
Symbol
fsck
tsrs
tcss
tcsh
tscl
tsch
tdsu
tdh
tr2
tf2
Min
0
20
20
1.0
66
66
40
15
-
-
Notes:
19. Data must be held for sufficient time to bridge the transition time of CCLK.
20. For fsck <1 MHz.
CS42L51
Max
6.0
-
-
-
-
-
-
-
100
100
Units
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
RST
tsrs
CS
tcss
tsch
tscl
tcsh
tr2
CCLK
tf2
tdsu tdh
CDIN
Figure 8. Control Port Timing - SPI Format
DS679A2
23
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