CS4228-KS 데이터 시트보기 (PDF) - Cirrus Logic

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CS4228-KS

24-Bit, 96 kHz Surround Sound Codec

Cirrus Logic 

CS4228

Serial Clock — SCLK

Pin 5, Bidirectional

Function:

Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins, and out of the SDOUT pin. The pin is an output

in master mode, and an input in slave mode.

In master mode, SCLK is configured as an output. MCLK is divided internally to generate SCLK at the

desired multiple of the sample rate.

In slave mode, SCLK is configured as an input. The serial clock can be provided externally, or the pin can

be grounded and the serial clock derived internally from MCLK.

The required relationship between the Left/Right clock, serial clock and serial audio data is defined by the

Serial Port Mode register. The options are detailed in Figures 9, 10, 11 and 12.

Left/Right Clock — LRCK

Pin 6, Bidirectional

Function:

The Left/Right clock determines which channel is currently being input or output on the serial audio data

output, SDOUT. The frequency of the Left/Right clock must be at the output sample rate, Fs. In Master

mode, LRCK is an output, in Slave Mode, LRCK is an input whose frequency must be equal to Fs and

synchronous to the Master clock.

Audio samples in Left/Right pairs represent simultaneously sampled analog inputs whereas Right/Left

pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock,

serial clock and serial data is defined by the Serial Port Mode register. The options are detailed in Figures

9, 10, 11 and 12.

Digital Ground - DGND

Pin 7, Inputs

Function:

Digital ground reference.

Digital Power - VD

Pin 8, Input

Function:

Digital power supply. Typically 3.3 VDC.

Digital Interface Power - VL

Pin 9, Input

Function:

Digital interface power supply. Typically 3.3 or 5.0 VDC. All digital output voltages and input thresholds

scale with VL.

DS307PP1

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