C8051F93X-C8051F92X 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F93X-C8051F92X

Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU

Silicon Laboratories 

C8051F93x-C8051F92x

SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection

Bit

7

6

5

4

3

2

1

0

Name

CP0RIE CP0FIE

CP0MD[1:0]

Type R/W

R

R/W

R/W

R

R

R/W

Reset

1

0

0

0

0

0

1

0

SFR Page = All Pages; SFR Address = 0x9D

Bit Name

Function

7

Reserved Reserved. Read = 1b, Must Write 1b.

6

Unused Unused.

Read = 0b, Write = don’t care.

5

CP0RIE Comparator0 Rising-Edge Interrupt Enable.

0: Comparator0 Rising-edge interrupt disabled.

1: Comparator0 Rising-edge interrupt enabled.

4

CP0FIE Comparator0 Falling-Edge Interrupt Enable.

0: Comparator0 Falling-edge interrupt disabled.

1: Comparator0 Falling-edge interrupt enabled.

3:2

Unused Unused.

Read = 00b, Write = don’t care.

1:0 CP0MD[1:0] Comparator0 Mode Select

These bits affect the response time and power consumption for Comparator0.

00: Mode 0 (Fastest Response Time, Highest Power Consumption)

01: Mode 1

10: Mode 2

11: Mode 3 (Slowest Response Time, Lowest Power Consumption)

Rev. 1.3

97

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