C8051F91X-C8051F90X 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F91X-C8051F90X

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

SFR Definition 12.6. EIP2: Extended Interrupt Priority 2

Bit

7

6

5

4

3

2

1

0

Name

PSPI1 PRTC0F PMAT PWARN

Type

R

R

R

R

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

SFR Page = All Pages; SFR Address = 0xF7

Bit Name

Function

7:4 Unused Unused.

Read = 0000b. Write = Don’t care.

3 PSPI1 Serial Peripheral Interface (SPI1) Interrupt Priority Control.

This bit sets the priority of the SPI1 interrupt.

0: SP1 interrupt set to low priority level.

1: SPI1 interrupt set to high priority level.

2 PRTC0F SmaRTClock Oscillator Fail Interrupt Priority Control.

This bit sets the priority of the SmaRTClock Alarm interrupt.

0: SmaRTClock Alarm interrupt set to low priority level.

1: SmaRTClock Alarm interrupt set to high priority level.

1 PMAT Port Match Interrupt Priority Control.

This bit sets the priority of the Port Match Event interrupt.

0: Port Match interrupt set to low priority level.

1: Port Match interrupt set to high priority level.

0 PWARN Supply Monitor Early Warning Interrupt Priority Control.

This bit sets the priority of the VDD/DC+ Supply Monitor Early Warning interrupt.

0: Supply Monitor Early Warning interrupt set to low priority level.

1: Supply Monitor Early Warning interrupt set to high priority level.

Rev. 1.0

129

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