C8051F38C-GMR 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F38C-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

Figure 3.9. QFN-32 Recommended PCB Land Pattern

Table 3.7. QFN-32 PCB Land Pattern Dimensions

Dimension

Min

Max

Dimension

Min

Max

C1

4.80

4.90

X2

3.20

3.40

C2

4.80

4.90

Y1

0.75

0.85

E

0.50 BSC

Y2

3.20

3.40

X1

0.20

0.30

Notes:

General:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

Solder Mask Design:

3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder

mask and the metal pad is to be 60 m minimum, all the way around the pad.

Stencil Design:

4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used

to assure good solder paste release.

5. The stencil thickness should be 0.125 mm (5 mils).

6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.

7. A 3x3 array of 1.0 mm openings on a 1.2mm pitch should be used for the center pad to assure

the proper paste volume.

Card Assembly:

8. A No-Clean, Type-3 solder paste is recommended.

9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small

Body Components.

Rev. 1.4

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