C8051F38C-GQR 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F38C-GQR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

SFR Definition 27.2. PCA0MD: PCA Mode

Bit

7

6

5

4

3

2

1

0

Name CIDL

WDTE WDLCK

CPS[2:0]

ECF

Type R/W

R/W

R/W

R

R/W

R/W

Reset

0

1

0

0

0

0

0

0

SFR Address = 0xD9; SFR Page = All Pages

Bit Name

Function

7

CIDL PCA Counter/Timer Idle Control.

Specifies PCA behavior when CPU is in Idle Mode.

0: PCA continues to function normally while the system controller is in Idle Mode.

1: PCA operation is suspended while the system controller is in Idle Mode.

6 WDTE Watchdog Timer Enable.

If this bit is set, PCA Module 4 is used as the watchdog timer.

0: Watchdog Timer disabled.

1: PCA Module 4 enabled as Watchdog Timer.

5 WDLCK Watchdog Timer Lock.

This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog

Timer may not be disabled until the next system reset.

0: Watchdog Timer Enable unlocked.

1: Watchdog Timer Enable locked.

4 Unused Read = 0b, Write = Don't care.

3:1 CPS[2:0] PCA Counter/Timer Pulse Select.

These bits select the timebase source for the PCA counter

000: System clock divided by 12

001: System clock divided by 4

010: Timer 0 overflow

011: High-to-low transitions on ECI (max rate = system clock divided by 4)

100: System clock

101: External clock divided by 8 (synchronized with the system clock)

11x: Reserved

0

ECF PCA Counter/Timer Overflow Interrupt Enable.

This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.

0: Disable the CF interrupt.

1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is

set.

Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the

contents of the PCA0MD register, the Watchdog Timer must first be disabled.

312

Rev. 1.4

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