M95512-DWCS3TP 데이터 시트보기 (PDF) - STMicroelectronics

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M95512-DWCS3TP

512 Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

M95512-W, M95512-R

5

Memory organization

The memory is organized as shown in Figure 7.

Figure 7. Block diagram

HOLD

W

S

C

D

Q

Control Logic

High Voltage

Generator

I/O Shift Register

Address Register

and Counter

Data

Register

Memory organization

Status

Register

Size of the

Read only

EEPROM

area

1 Page

X Decoder

AI01272C

Doc ID 11124 Rev 13

15/48

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