CS48LV13-ENZR 데이터 시트보기 (PDF) - Cirrus Logic

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CS48LV13-ENZR

Ultralow Power HD Voice Processors, Featuring SoundClear® Technology

Cirrus Logic 

5.1 I/O Pin Characteristics

5.1 I/O Pin Characteristics

Input and output levels and associated power supply voltage are shown in Table 5-1. Logic levels should not exceed the

corresponding power supply voltage. Typical hysteresis for VL inputs is 250 mV.

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Pin Name

DAO_D1

DAI_D2

DAO_D2

DAI_D1

SCLK

LRCLK

CLOCK

MCLK

MISO/SDA

MOSI

CLK/SCL

CS

DBCK

DBDA

RESET

INT

BUSY/

I2C_SELECT

Table 5-1. I/O Pin Characteristics

I/O

Voltage

Reference

Internal

Termination

Driver

Receiver

I/O

VL

Programmable pull-up

CMOS

CMOS, with hysteresis

I/O

VL

Programmable pull-up

CMOS

CMOS, with hysteresis

I/O

VL

Programmable pull-up

CMOS

CMOS, with hysteresis

I/O

VL

Programmable pull-up

CMOS

CMOS, with hysteresis

I/O

VL

Programmable pull-up

CMOS

CMOS, with hysteresis

I/O

VL

Programmable pull-up

CMOS

CMOS, with hysteresis

I

VL

—

—

CMOS, with hysteresis

I/O

VL

Programmable pull-up

CMOS

CMOS, with hysteresis

I/O

VL

Programmable pull-up CMOS/open drain

CMOS, with hysteresis

I/O

VL

Programmable pull-up

CMOS

CMOS, with hysteresis

I/O

VL

Programmable pull-up CMOS/open drain

CMOS, with hysteresis

I/O

VL

Programmable pull-up

CMOS

CMOS, with hysteresis

I/O

VL

Programmable pull-up CMOS/open drain

CMOS, with hysteresis

I/O

VL

Programmable pull-up CMOS/open drain

CMOS, with hysteresis

I

VL

Pull-up

—

CMOS, with hysteresis

O

VL

Programmable pull-up CMOS/open drain

CMOS, with hysteresis

I/O

VL

Programmable pull-up CMOS/open drain

CMOS, with hysteresis

23

DS1057F1

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