CS48LV13-ENZR 데이터 시트보기 (PDF) - Cirrus Logic
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CS48LV13-ENZR Datasheet PDF : 26 Pages
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4.3 Power Supply Characteristics—1.0 V Power Dissipation
4.3 Power Supply Characteristics—1.0 V Power Dissipation
Test Conditions (unless otherwise specified): VD,VPLL=1.0 V, VL=1.8 V, GND = 0 V; all voltages with respect to GND.
TA = +25°C.
Core and I/O Operating1
RESET Active3
Hibernate Mode4
Sleep Mode5
Parameters
VD + VPLL2
VL
VD + VPLL2
VL
VD + VPLL2
VL
VD + VPLL2
VL
Typical
9.5
0.8
1.8
1.5
11
0.147
45
0.147
Units
mA
mA
mA
A
A
A
A
A
1.Characterized with O/S and MP3 decode running at 80 MHz, 6 MHz CLOCK driving PLL, MCLK slave, I²S data delivery.
2.VPLL exists only on the QFN package.The WLCSP package combines VD and VPLL into a single VD pin.
3.Characterized with RESET driven low, CLOCK pin of CS48LV12/13 gated off, and all inputs to CS48LV12/13 driven to VL.
4.The low-power mode used in this example is Hibernate mode. Characterized with DSP core halted, all memory banks powered down, PLL powered
down, and all internal clock domains gated off, CLOCK pin of CS48LV12/13 gated off, and all inputs to CS48LV12/13 driven to VL.
5.The low-power mode used in this example is Sleep mode. Characterized with DSP core halted, all memory banks powered up, PLL powered down,
all internal clock domains gated off, CLOCK pin of CS48LV12/13 gated off, and all inputs to CS48LV12/13 driven to VL.
4.4 Power Supply Characteristics—1.2 V Power Dissipation
Test Conditions (unless otherwise specified): VD,VPLL=1.2 V, VL=1.8 V, GND = 0 V; all voltages with respect to GND.
TA = +25°C.
Core and I/O Operating1
RESET Active3
Hibernate Mode4
Sleep Mode5
Parameters
VD + VPLL2
VL
VD + VPLL2
VL
VD + VPLL2
VL
VD + VPLL2
VL
Typical
12.0
0.8
3.3
1.5
17
0.147
75
0.147
Units
mA
mA
mA
A
A
A
A
A
1.Characterized with O/S and MP3 decode running at 80 MHz, 6 MHz CLOCK driving PLL, MCLK slave, I²S data delivery.
2.VPLL exists only on the QFN package. The WLCSP package combines VD and VPLL into a single VD pin.
3.Characterized with RESET driven low, CLOCK pin of CS48LV12/13 gated off, and all inputs to CS48LV12/13 driven to VL.
4.The low-power mode used in this example is Hibernate mode. Characterized with DSP core halted, all memory banks powered down, PLL powered
down, and all internal clock domains gated off, CLOCK pin of CS48LV12/13 gated off, and all inputs to CS48LV12/13 driven to VL.
5.The low-power mode used in this example is Sleep mode. Characterized with DSP core halted, all memory banks powered up, PLL powered down,
all internal clock domains gated off, CLOCK pin of CS48LV12/13 gated off, and all inputs to CS48LV12/13 driven to VL.
DS1057F1
14
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