74LVQ00M 데이터 시트보기 (PDF) - STMicroelectronics

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74LVQ00M

LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE

STMicroelectronics 

74LVQ00

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)

Test Condition

Value

Symbol

Parameter

VCC

(V)

TA = 25°C

-40 to 85°C -55 to 125°C Unit

Min. Typ. Max. Min. Max. Min. Max.

tPLH tPHL Propagation Delay 2.7

Time

3.3(*)

. 6.0 11.0

12.0

14.0

5.5 8.0

ns

9.0

10.0

tOSLH

tOSHL

Output To Output 2.7

Skew Time (note1,

2)

3.3(*)

0.5 1.0

1.0

1.0

0.5 1.0

1.0

1.0 ns

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-

ing in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)

2) Parameter guaranteed by design

(*) Voltage range is 3.3V ± 0.3V

CAPACITIVE CHARACTERISTICS

Test Condition

Value

Symbol

Parameter

VCC

(V)

TA = 25°C

-40 to 85°C -55 to 125°C Unit

Min. Typ. Max. Min. Max. Min. Max.

CIN Input Capacitance 3.3

4

pF

CPD Power Dissipation

Capacitance (note 3.3

fIN = 10MHz

24

pF

1)

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without

load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per gate)

TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)

RL = 500Ω or equivalent

RT = ZOUT of pulse generator (typically 50Ω)

4/8

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