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전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

STM32F103RC 데이터 시트보기 (PDF) - STMicroelectronics

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STM32F103RC Datasheet PDF : 123 Pages
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STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
Figure 54. Typical connection diagram using the ADC
RAIN(1)
AINx
VAIN
Cparasitic
VDD
VT
0.6 V
VT
0.6 V
IL±1 µA
STM32F103xx
Sample and hold ADC
converter
RADC(1)
12-bit
converter
CADC(1)
ai14150c
1. Refer to Table 58 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 55 or Figure 56,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 55. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F103xx
VREF+
(see note 1)
1 µF // 10 nF
1 µF // 10 nF
VDDA
VSSA /VREF–
(see note 1)
ai14388b
1. VREF+ and VREF– inputs are available only on 100-pin packages.
Doc ID 14611 Rev 7
101/123

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