ZPSD403A2V-C-20UI 데이터 시트보기 (PDF) - STMicroelectronics

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ZPSD403A2V-C-20UI

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics 

PSD4XX Family

9.0

The PSD4XX

Architecture

(cont.)

9.1.1.5 The ZPLD Power Management

The ZPLD implements a Zero Power Mode, which provides considerable power savings

for low to medium frequency operations. To enable this feature, the ZPLD Turbo bit in the

Power Management Mode Register 0 (PMMR0) has to be turned off.

If none of the inputs to the ZPLD are switching for a time period of 90ns, the ZPLD puts

itself into Zero Power Mode and the current consumption is minimal. The ZPLD will

resume normal operation as soon as one or more of the inputs change state.

Two other features of the ZPLD provide additional power savings:

1. Clock Disable:

Users can disable the clock input to the ZPLD and/or macrocells,thereby reducing

AC power consumption.

2. Product Term Disable:

Unused product terms in the ZPLD are disabled by the PSDsoft Software

automatically for further power savings.

The ZPLD power configuration is described in the Power Management Unit section.

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