V300PSC-33REVA0 데이터 시트보기 (PDF) - QuickLogic Corporation
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V300PSC-33REVA0 Datasheet PDF : 20 Pages
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V300PSC
Table 14: Local Bus Timing Parameters for Vcc = 5 Volts +/- 5%
33MHz
# Symbol
Description
Notes Min Max Units
1 TC LCLK period
2 TCH LCLK high time
1
3 TCL LCLK low time
1
4 TSU Synchronous input setup
2
4a TSU Synchronous input setup (BTERM)
4b TSU Synchronous input setup (data)
5 TH Synchronous input hold
6 TCOV LCLK to output valid delay
3
6a
TCOV
LCLK to output valid delay (address, data,
byte enable, parity)
30
ns
12
ns
12
ns
7
ns
4
ns
5
ns
2 ns
3 14 ns
3 15 ns
7 TCZO LCLK to output driving delay
8 TCOZ LCLK to high impedance delay
3 15 ns
4
3 15 ns
Notes:
1. Measured at 1.5V.
2. All local bus signals except those in 4a, 4b, 4c.
3. All local bus signals except those in 6a.
4. READY, BLAST, ADS are driven to high impedance at the falling edge of LCLK.
Table 15: ALE Timing Parameters for Vcc = 5 Volts +/- 5%
# Symbol
Description
1 TALE ALE Pulse Width
2 TASU Address setup to ALE falling (ALE as output)
3 TAH Address hold from ALE falling (ALE as output)
33MHz
Min Max Units
TCH-4
ns
TCH-5
ns
TCL-5
ns
16
V300PSC Data Sheet Rev 1.1
Copyright © 1997, V3 Semiconductor Corp.
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