CS8900 データシートの表示（PDF） - Cirrus Logic

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CS8900

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

5.6 StreamTransfer

Overview

The CS8900 supports an optional feature,

StreamTransfer, that can reduce the amount of

CPU overhead associated with frame reception.

StreamTransfer works during periods of high re-

ceive activity by grouping multiple receive

events into a single interrupt, thereby reducing

the number of receive interrupts to the host proc-

essor. During periods of peak loading,

StreamTransfer will eliminate 7 out of every 8

interrupts, cutting interrupt overhead by up to

87%.

Configuring the CS8900 for StreamTransfer

StreamTransfer is enabled by setting the StreamE

bit along with either the AutoRxDMAE bit or the

RxDMAonly bit in register Receiver Configura-

tion (register 3). (StreamTransfer must not be

selected unless either one of AutoRxDMAE or

RxDMA-only is selected.) StreamTransfer only

applies to "good" frames (frames of legal length

with valid CRC). Therefore, the RxOKA bit and

the RxOKiE bit must both be set. Finally,

StreamTransfer works on whole packets and is

not compatible with early interrupts. This re-

quires that the RxDestiE bit and the Rx128iE bit

both be clear.

Register Name

Register 3, RxCFG

Register 5, RxCTL

Register B, BufCFG

Bit

Bit Name Value

7

StreamE

1

8

RxOKiE

1

9

RxDMAonly

1

or

or

or

A

AutoRxDMA

1

8

RxOKA

1

7

RxDMAiE

1

F

RxDestiE

0

B

Rx128iE

0

Table 5.10. Stream Transfer Configuration

Table 5.10 summarizes how to configure the

CS8900 for StreamTransfer.

DS150PP2

StreamTransfer Operation

When StreamTransfer is enabled, the CS8900

will initiate a StreamTransfer cycle whenever

two or more frames with the following charac-

teristics are received:

1. pass the Destination Address filter;

2. are of legal length with valid CRC; and,

3. are spaced "back-to-back" (between 9.6 and

52 µs apart).

During a StreamTransfer cycle the CS8900 does

the following:

• delays the normal RxOK interrupt associated

with the first receive frame;

• switches to receive DMA mode;

• transfers up to eight receive frames into host

memory via DMA;

• updates the DMA Start-of-Frame register

(PacketPage base + 0026h);

• updates the DMA Frame Count register

(PacketPage base + 0028h);

• updates DMA Byte Count register (Packet-

Page base + 002Ah);

• sets the RxDMAFrame bit (Register C,

BufEvent, Bit 7); and,

• generates an RxDMAFrame interrupt.

Keeping StreamTransfer Mode Active

When the CS8900 initiates a StreamTransfer cy-

cle, it will continue to execute cycles as long as

the following conditions hold true:

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