CS8900 データシートの表示（PDF） - Cirrus Logic

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CS8900

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Register 14: Line Status (LineST, Read-only)

Address: PacketPage base + 0134h

F

E

D

C

B

CRS

PolarityOK

A

9

8

7

6

5-0

10BT

AUI

LinkOK

010100

LineST reports the status of the Ethernet physical interface.

BIT NAME

DESCRIPTION

5-0 010100

These bits provide an internal address used by the CS8900 to identify this as the Line

Status Register. When reading this register, these bits will be 010100, where the LSB

corresponds to Bit 0.

7

LinkOK

If set, the 10BASE-T link has not failed. When clear, the link has failed, either because

the CS8900 has just come out of reset, or because the receiver has not detected any

activity (link pulses or received packets) for at least 50 ms.

8

AUI

If set, the CS8900 is using the AUI.

9

10BT

If set, the CS8900 is using the 10BASE-T interface.

C

PolarityOK

If set, the polarity of the 10BASE-T receive signal (at the RXD+ / RXD- inputs) is

correct. If clear, the polarity is reversed. If PolarityDis (Register 19, TestCTL, Bit C) is

set, then the polarity is automatically corrected, if needed. The PolarityOK status bit

shows the true state of the incoming polarity independent of the PolarityDis control bit.

Thus, if PolarityDis is clear and PolarityOK is clear, then the receive polarity is inverted,

and corrected.

E

CRS

This bit tells the host the status of an incoming frame. If CRS is set, a frame is currently

being received. CRS remains asserted until the end of frame (EOF). At EOF, CRS goes

inactive in about 1.3 to 2.3 bit times after the last low-to-high transition of the recovered

data.

This register’s initial state after reset is: 0X0X 00XX X001 0100

DS150PP2

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