C8051F521-C-IM データシートの表示（PDF） - Silicon Laboratories

部品番号

コンポーネント説明

メーカー

C8051F521-C-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

1.6. Programmable Comparator

C8051F52x/F52xA/F53x/F53xA devices include a software-configurable voltage comparator with an input

multiplexer. The comparator offers programmable response time and hysteresis and an output that is

optionally available at the Port pins: a synchronous “latched” output (CP0). The comparator interrupt may

be generated on rising, falling, or both edges. When in IDLE or SUSPEND mode, these interrupts may be

used as a “wake-up” source for the processor. The Comparator may also be configured as a reset source.

A block diagram of the comparator is shown in Figure 1.8.

Port I/O

Pins

VDD

Interrupt

Logic

+

-

GND

D SET Q

Q CLR

D SET Q

Q CLR

(SYNCHRONIZER)

Reset

Decision

Tree

CP0

(synchronous output)

CP0A

(asynchronous output)

Figure 1.8. Comparator Block Diagram

1.7. Voltage Regulator

C8051F52x/F52xA/F53x/F53xA devices include an on-chip low dropout voltage regulator (REG0). The

input to REG0 at the VREGIN pin can be as high as 5.25 V. The output can be selected by software to 2.1 or

2.6 V. When enabled, the output of REG0 powers the device and drives the VDD pin. The voltage regulator

can be used to power external devices connected to VDD.

1.8. Serial Port

The C8051F52x/F52xA/F53x/F53xA family includes a full-duplex UART with enhanced baud rate configu-

ration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and

makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.

Rev. 1.4

23

Share Link: