CS5376-BS データシートの表示（PDF） - Cirrus Logic

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CS5376-BS

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

Modulator Interface

MCLK - Modulator Clock Output, pin 13

The CS5376 outputs a clock to operate the CS5372 modulator. The clock frequency is

selectable, nominal frequency 2.048 MHz.

MCLK/2 - Modulator Clock Divided by 2 Output, pin 12

The CS5376 outputs a slower clock to operate the CS5321 modulator. The clock frequency is

selectable, nominal frequency 1.024 MHz.

MSYNC - Modulator Sync Output, pin 14

A transition from logic low to high reinitializes the modulator timing to be synchronous with

the timing of the CS5376. Generated from the SYNC input signal.

MDATA[4:1] - Modulator Data Input, pin 15, 17, 19, 21

Modulator data is presented in a one-bit serial data stream (one’s density) at a rate dictated by

the rate of the MCLK signal. 512 kbit and 256 kbit are typical MDATA rates.

MFLAG[4:1] - Modulator Flag Input, pin 16, 18, 20, 22

Logic input which transitions from low to high to indicate that the modulator is in an unstable

condition due to an over-ranged signal on its analog input.

Serial Data Output Port

SDTKI - Serial Data Chip Select Input, pin 64

Pulsed input signal which will initiate SDRDYZ signaling.

SDRDY - Serial Data Ready Output, pin 61

Signal which goes low to indicate that 32-bit conversion words are available to be clocked out

of the SDDAT pin.

SDCLK - Serial Data Clock Input, pin 62

Input clock which determines the rate at which the SDDAT bits are output.

SDDAT - Serial Data Output, pin 60

Serial data output for conversion words from the CS5376. Formatted to output a 32-bit digital

word consisting of one status byte followed by a three byte conversion word.

SDTKO - Serial Data Chip Select Output, pin 63

Output signal which indicates the current transaction has been completed.

DS256PP1

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