CS5501 データシートの表示（PDF） - Cirrus Logic
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CS5501 Datasheet PDF : 54 Pages
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CS5501 CS5503
CS5501/CS5503
10 Ω
+5V
Analog
Supply
0.1 µF
14
VA+
0.1 µF
15
VD+
13
CAL
3
CLKIN
Analog
Signal
Source
0 VREF
or
±VREF
+5V
Analog
Supply
Calibration
Control
Bipolar/
Unipolar
Input Select
4
SC1
2
CLKOUT
17
SC2
SLEEP 11
CS5501
CS5503
12
BP/UP
1
MODE
200 Ω∗
9
AIN
19
SCLK
0.0047 µF NPO
20
SDATA
Voltage
Reference
+2.5V 10
VREF
8
AGND
18
DRDY
16
CS
DGND 5
-5V
Analog
Supply
0.1 µF
VA-
VD-
7
6
10 Ω
0.1 µF
Optional
Clock
Source
Sleep Mode
Control
Output
Mode Select
Serial
Data
Interface
Control
Logic
Unused Logic Inputs
must be connected
to DGND or VD+
* Recommended to
reduce high
frequency noise
Figure 15. Typical Connection Diagram
age reference, and the analog signal conditioning
circuitry from the same primary source. If sepa-
rate supplies are used, it is recommended that the
CS5501/CS5503 be powered up first. If a com-
mon power source is used for the analog signal
conditioning circuitry as well as the A/D con-
verter, this power source should be applied
before application of power to the digital logic
supply.
The CS5501/CS5503 exhibit good power supply
rejection for frequencies within the passband (dc
to 10 Hz). Any small offset or gain error caused
by long term drift of the power supplies can be
removed by recalibration. Above 10 Hz the digi-
tal filter will provide additional rejection. When
the benefits of the digital filter are added to the
regular power supply rejection the effects of line
frequency variations (60 Hz) on the power sup-
plies will be reduced greater than 120 dB. If the
supply voltages for the CS5501/CS5503 are gen-
erated with a dc-dc converter the operating
frequency of the dc-dc converter should not oper-
ate at the sampling frequency of the
CS5501/CS5503 or at integer multiples thereof.
At these frequencies the digital filter will not aid
in power supply rejection. See Anti-Alias Consid-
erations section of this data sheet.
2266
DS31F54
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