STM32L151V6H6TR(2013) データシートの表示（PDF） - STMicroelectronics

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STM32L151V6H6TR
(Rev.:2013)

Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3, 128KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC

STMicroelectronics 

Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order).

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or

source up to ±20 mA (with the non-standard VOL/VOH specifications given in Table 43.

in the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 6.2:

● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run

consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating

IVDD (see Table 12).

● The sum of the currents sunk by all the I/Os on VSS plus the maximum Run

consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating

IVSS (see Table 12).

Output voltage levels

Unless otherwise specified, the parameters given in Table 43 are derived from tests

performed under ambient temperature and VDD supply voltage conditions summarized in

Table 14. All I/Os are CMOS and TTL compliant.

Table 43. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max Unit

VOL(1)(2)

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

IIO = +8 mA

0.4

VOH(3)(2)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

2.7 V < VDD < 3.6 V

2.4

VOL (1)(4)

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

VOH (3)(4)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

IIO =+ 4 mA

0.45

1.65 V < VDD <

V

2.7 V

VDD-0.45

VOL(1)(4)

Output low level voltage for an I/O pin

when 4 pins are sunk at same time

IIO = +20 mA

1.3

VOH(3)(4)

Output high level voltage for an I/O pin

when 4 pins are sourced at same time

2.7 V < VDD < 3.6 V

VDD-1.3

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12

and the sum of IIO (I/O ports and control pins) must not exceed IVSS.

2. Tested in production.

3. The IIO current sourced by the device must always respect the absolute maximum rating specified in

Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.

4. Based on characterization data, not tested in production.

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Doc ID 17659 Rev 8

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