STM32F100VBH7BTR(2010) データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

メーカー

STM32F100VBH7BTR
(Rev.:2010)

Low & medium-density value line, advanced ARM-based 32-bit MCU with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces

STMicroelectronics 

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 30. EMI characteristics

Symbol Parameter

Conditions

Monitored

frequency band

Max vs. [fHSE/fHCLK]

Unit

8/24 MHz

0.1 MHz to 30 MHz

9

SEMI

Peak level

VDD 3.3 V, TA 25°C,

LQFP100 package

compliant with

30 MHz to 130 MHz

130 MHz to 1GHz

17

16

dBµV

IEC 61967-2

SAE EMI Level

4

-

5.3.11

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

Table 31. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class

Maximum

value(1)

Unit

VESD(HBM)

Electrostatic discharge

voltage (human body model)

TA +25 °C

conforming to JESD22-A114

2

VESD(CDM)

Electrostatic discharge

TA +25 °C

voltage (charge device model) conforming to JESD22-C101

II

TBD

V

TBD

1. Based on characterization results, not tested in production.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

● A supply overvoltage is applied to each power supply pin

● A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD78 IC latch-up standard.

Table 32. Electrical sensitivities

Symbol

Parameter

Conditions

LU

Static latch-up class TA +105 °C conforming to JESD78

Class

TBD

Doc ID 16455 Rev 2

53/84

Share Link: